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SY58611U
3.2Gbps Precision, LVDS 2:1 MUX with Internal Termination and Fail Safe Input
General Description
The SY58611U is a 2.5V, high-speed, fully differential LVDS 2:1 MUX capable of processing clocks up to 2.5GHz and data up to 3.2Gbps. SY58611U is optimized to provide a buffered output of the selected input with less than 20ps of skew and less than 10pspp total jitter. Patented MUX Isolation design reduces crosstalk and provides superior signal integrity. The differential inputs include Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC- or DC-coupled) as small as 100mVPK (200mVpp) without any levelshifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated reference voltage (VREF-AC) is provided to bias the VT pin. The output is LVDS compatible, with rise/fall times guaranteed to be less than 120ps. The SY58611U operates from a 2.5V 5% supply and is guaranteed over the full industrial temperature range (-40C to +85C). For applications that require CML or LVPECL output, consider the SY58609U and SY58610U, 2:1 MUX with 400mV and 800mV output swings respectively. The SY58611U is part of Micrel's high-speed, Precision Edge(R) product line. Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Selects between two sources and provides buffered copy of the selected input signal * Fail Safe Input - Prevents output from oscillating when input is invalid or removed * Guaranteed AC performance over temperature and voltage: - DC-to > 3.2Gbps throughput - <420ps typical propagation delay (IN-to-Q) - <120ps rise/fall times * Unique, patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) * Unique, patented MUX input isolation design minimizes adjacent channel crosstalk * Ultra-low jitter design - <1psRMS cycle-to-cycle jitter - <10psPP total jitter - <1psRMS random jitter - <10psPP deterministic jitter * 2.5V 5% power supply operation * Industrial temperature range: -40C to +85C * Available in 16-pin (3mm x 3mm) MLF(R) package
Functional Block Diagram
Applications
* * * * All SONET clock distribution Fibre Channel clock and data distribution Gigabit Ethernet clock or data distribution Backplane distribution
Markets
* * * *
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
DataCom and Telecom Storage ATE Test and Measurement
March 2007
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SY58611U
Ordering Information(1)
Part Number SY58611UMG SY58611UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type MLF-16 MLF-16
Operating Range Industrial Industrial
Package Marking 611U with Pb-Free bar-line indicator 611U with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
Truth Table
SEL 0 1 Output IN0 Selected IN1 Selected
16-Pin MLF(R) (MLF-16)
Pin Description
Pin Number 1, 4 Pin Name VT0, VT1 Pin Function Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" subsection. Reference Voltage: These outputs bias to VCC-1.2V. They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is 0.5mA. See "Input Interface Applications" subsection. Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-Coupled differential signals as small as 100mV (200mVPP). Each pin of the pairs internally terminates with 50 to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See "Input Interface Applications" subsection. Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCC pins as possible. LVDS Differential Output Pair: Differential buffered output copy of the selected input signal. The output swing is typically 325mV. Normally terminated 100 across the output (Q and /Q). See "LVDS Output Interface Applications" subsection. Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pin. No connect.
2, 3
VREF-AC0, VREF-AC1
5, 6 15, 16
IN1, /IN1 IN0, /IN0
7
SEL
8, 13 9, 12
VCC /Q, Q
10, 11 14
GND, Exposed pad NC
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SY58611U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................... -0.5V to +4.0V Input Voltage (VIN) .......................................-0.5V to VCC LVDS Output Current (IOUT)..................................10mA Input Current Source or Sink Current on (IN, /IN) ...............50mA Current (VREF) Source or sink current on VREF-AC(4) ..............0.5mA Maximum operating Junction Temperature ......... 125C Lead Temperature (soldering, 20sec.) .................. 260C Storage Temperature (Ts) ....................-65C to +150C
Operating Ratings(2)
Supply Voltage (VCC)..................... +2.375V to +2.635V Ambient Temperature (TA) ................... -40C to +85C Package Thermal Resistance(3) MLF(R) Still-air (JA) ............................................ 60C/W Junction-to-Board (JB)......................... 33C/W
DC Electrical Characteristics(5)
TA = -40C to +85C unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VREF-AC VT_IN
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN (max) is specified when VT is floating.
Parameter Power Supply Voltage Range Power Supply Current Input Resistance (IN-to-VT, /IN-to-VT) Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing (|IN - /IN|) Input Voltage Threshold that Triggers FSI AC Reference Voltage Voltage from Input to VT
Condition No load, max. VCC
Min 2.375 45 90 1.2 0.2
Typ 2.5 40 50 100
Max 2.625 60 55 110 VCC VIH-0.1 1.0
Units V mA V V V V
see Figure 3a, Note 6 see Figure 3b
0.1 0.2 30
100 VCC-1.0 1.28
mV V V
IVREF-AC = + 0.5mA
VCC-1.3
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SY58611U
LVDS Output DC Electrical Characteristics(7)
VCC = +2.5V 5%, RL = 100 across the output pair; TA = -40C to +85C, unless otherwise stated.
Symbol VOUT VDIFF_OUT VOCM VOCM Parameter Output Voltage Swing (Q, /Q) Differential Output Voltage Swing |Q-/Q| Output Common Mode Voltage (Q, /Q) Change in Common Mode Voltage (Q, /Q) Condition See Figure 3a See Figure 3b See Figure 5b See Figure 5b Min 250 500 1.125 -50 Typ 325 650 1.20 1.275 50 Max Units mV mV V mV
LVTTL/CMOS DC Electrical Characteristics(7)
VCC = 2.5V 5%; TA = -40C to + 85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Notes: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125 -300
30
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SY58611U
AC Electrical Characteristics(8)
VCC = +2.5V 5%, RL = 100 across the output pair; Input tr/tf < 300ps, TA = -40C to +85C, unless otherwise stated.
Symbol fMAX tPD Parameter Maximum Frequency Propagation Delay SEL-to-Q tSkew tJitter Input-to-Input Skew Part-to-Part Skew Data Clock tr, tf Random Jitter Deterministic Jitter Cycle-to-Cycle Jitter Total Jitter Output Rise/Fall Times (20% to 80%) Duty Cycle
Notes: 8. 9. High-frequency AC-parameters are guaranteed by design and characterization. Input-to-Input skew is the time difference between the two inputs and one output, under identical input transitions.
Condition NRZ Data VOUT > 200mV IN-to-Q VIN: 100mV-200mV VIN: > 200mV Note 9, 10 Note 11 Note 12 Note 13 Note 14 Note 15 At full output swing. Differential I/O Clock
Min 3.2 2.5 190 150 150
Typ 3 330 280 5
Max
Units Gbps GHz
470 420 450 20 150 1 10 1 10
ps ps ps ps ps psRMS psPP psRMS psPP ps %
40 47
80
120 53
10. Input-to-Input Skew is included in IN-to-Q propagation delay. 11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at the edges at the respective inputs. 12. Random jitter is measured with a K28.7 pattern, measured at fMAX. 13. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern. 14. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn -Tn+1, where T is the time between rising edges of the output signal. 15. Total jitter definition: with an ideal clock input frequency of fMAX (device), no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value.
12 23
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SY58611U function will eliminate a metastable condition and latch the output to the last valid state. No ringing and no undetermined state will occur at the output under these conditions. The output recovers to normal operation once the input signal returns to a valid state with a typical swing greater than 30mV. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for detailed information.
Functional Description
Fail-Safe Input (FSI) The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the output when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Refer to Figure 1b. Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing such that the voltage swing across the input pair is significantly less than 100mV, FSI
Timing Diagrams
Figure 1a. Propagation Delay
Figure 1b. Fail-Safe Feature
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SY58611U
Figure 1c. SEL-to-Q Delay
Input Stage
Figure 2. Simplified Differential Input Buffer
Single-Ended and Differential Swings
Figure 3a. Single-Ended Swing
Figure 3b. Differential Swing
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SY58611U
Typical Characteristics
VCC = 2.5V, GND = 0V, VIN = 100mV, RL = 100 across the output pair, TA = 25C, unless otherwise stated.
March 2007
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SY58611U
Functional Characteristics
VCC = 2.5V, GND = 0V, VIN = 325mV, RL = 100 across the output pair, TA = 25C, unless otherwise stated.
March 2007
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SY58611U
Functional Characteristics (continued)
VCC = 2.5V, GND = 0V, VIN = 325mV, RL = 100 across the output pair, TA = 25C, unless otherwise stated.
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SY58611U
Input Interface Applications
Figure 4a. CML Interface (DC-Coupled)
Option: May connect VT to VCC
Figure 4b. CML Interface (AC-Coupled)
Figure 4c. LVPECL Interface (DC-Coupled)
Figure 4d. LVPECL Interface (AC-Coupled)
Figure 4e. LVDS Interface
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SY58611U
LVDS Output Interface Applications
LVDS specifies a small swing of 325mV typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in the ground between and LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.
Figure 5b. LVDS Common Mode Measurement
Figure 5a. LVDS Differential Measurement
Related Products and Support Documentation
Part Number SY58609U SY58610U HBW Solutions Function 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input 3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input New Products and Termination Application Notes Data Sheet Link http://www.micrel.com/_PDF/HBW/sy58609u.pdf http://www.micrel.com/_PDF/HBW/sy58610u.pdf http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml
March 2007
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Micrel, Inc.
SY58611U
Package Information
16-Pin (3mm x 3mm) MLF(R) (MLF-16)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2007 Micrel, Incorporated.
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